1. Field of the Invention
The present invention relates to a method of protecting the corner of a shallow trench isolation region and more particularly to a process for forming shallow trench isolation region with corner protection layer.
2. Description of the Related Art
Recently, as the manufacturing techniques of semiconductor integrated circuits develop, the number of devices in a chip was increased. The size of the device decreases as the degree of integration increases. The line width used in manufacturing lines has decreased from sub-micron to quarter-micron, or even smaller. Regardless of the reduction of the size of the device, adequate insulation or isolation must be formed among individual devices in the chip so that good element characteristics can be achieved. This technique is called device isolation technology. The main object is to form an isolation region, reducing the size of the isolation as much as possible while assuring good isolation effect to allow larger chip space for more devices.
Among different device isolation techniques, LOCOS and shallow trench isolation region manufacturing methods are the two most used methods. In particular, as the latter has a small isolation region and can keep the substrate level after the process is finished, it is the semiconductor manufacturing method obtaining the most attention.
The conventional manufacturing process for shallow trench isolation region is shown in the cross sections of FIG. 1A to 1D.
In FIG. 1A, a pad oxide layer 12 is formed on a silicon substrate 10 using thermal oxidation and a silicon nitride layer 14 is deposited on the pad oxide layer 12 using CVD. Next, a photoresist layer 16 is coated on the silicon nitride layer 14 and is patterned using photolithography to expose the portion where the device isolation region is to be formed. Silicon nitride layer 14 and pad oxide layer 12 are etched sequentially using the photoresist layer 16 as a mask.
In FIG. 1B, after photoresist layer 16 is removed with adequate solution, and silicon nitride layer 14 and pad oxide layer 12 are used as a mask to etch silicon substrate 10 to form a trench 20 inside, thereby defining the active region of the device. Subsequently, thermal oxidation is performed to grow a thin silicon oxide layer as the lining oxide layer 24 on the bottom and sidewall of the trench 20. However, when silicon dioxide is formed, the stress is concentrated on the curvature region of a smaller radius, and the corner 22 of trench 20 is a sharp curvature of small radius, the growth rate of the silicon dioxide at the corner 22 of the trench 20 is slower, so that the lining oxide layer 24 at the corner 22 of the trench 20 is very thin.
Next, chemical vapor deposition is performed, for example using O3 and TEOS as a reactant to form oxide layer 26, filling the trench 20 and covering the surface of the silicon nitride layer 14.
In FIG. 1C, chemical mechanical polishing (CMP) is then performed, wherein the part of oxide layer 26 higher than the surface of the silicon nitride layer 14 is removed to form the shallow trench isolation region 26a with a level surface. Subsequently, a suitable etching method is used to remove the silicon nitride layer 14 and pad oxide layer 12 in order to complete shallow trench isolation, and the structure shown in FIG. 1D is obtained.
Because the properties of the shallow trench isolation region 26a are similar to those of the pad oxide layer 12, when etchant is used to dip pad oxide layer 12, the shallow trench isolation region 26a is inevitably etched so that the corner 22 of the trench 20 is exposed and an indentation 30 is formed adjacent to the corner 22 of the trench 20.
Thus, when the gate oxide layer and gate conductive layer are formed later, the conductive layer deposited in the indentation 30 is not easily removed and a short circuit between the adjacent transistors is easily formed. In addition, since the gate oxide layer at the corner 22 of the trench 20 is thinner than other places, a parasitic transistor is then formed. This phenomenon is equivalent to two transistors with gate oxide layers of different thickness in parallel. When current goes through this parasitic transistor, as the curvature radius of the corner 22 of the trench 20 is small, the electric fields concentrate and the Fowler-Nordheim current increases, hence the insulating property of the gate oxide layer of the corner 22 degrades, resulting in abnormal element characteristics. For example, there is a kink effect in I-V curvature of Id and Vg, which generates a double hump.